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chore(macros/ex02): used homebrew BV macro and fixed ex02 to use timer interupt

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This commit is contained in:
Maix0 2026-04-19 15:38:04 +02:00
parent 508ba6e857
commit 29b0d72ff9
17 changed files with 191 additions and 200 deletions
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6
ex00/include/interupt.h
View file

@ -3,12 +3,14 @@
#include <avr/io.h>
#include "mystd.h"
static inline void my_sei(void) {
SREG |= _BV(SREG_I);
SREG |= BV(SREG_I);
}
static inline void my_cli(void) {
SREG &= ~_BV(SREG_I);
SREG &= ~BV(SREG_I);
}
#endif /* INTERUPT_H */

2
ex00/include/mystd.h
View file

@ -14,4 +14,6 @@ typedef uint8_t bool;
#define NULL ((void*)0)
#define BV(bit) (1 << bit)
#endif /* MYSTDINT_H */

38
ex00/include/timer0.h
View file

@ -8,30 +8,30 @@
static inline void t0_init_fpwm_3(e_timer_prescaler prescaler) {
// Fast PWM (8-bit): WGM22:0 = 0b011
TCCR0A = _BV(WGM00) | _BV(WGM01);
TCCR0A = BV(WGM00) | BV(WGM01);
// reset to zero -> timer off
TCCR0B &= ~(_BV(CS02) | _BV(CS01) | _BV(CS00));
TCCR0B &= ~(BV(CS02) | BV(CS01) | BV(CS00));
// set the correct prescaler
switch (prescaler) {
case (PRESCALER_1): {
TCCR0B |= (_BV(CS00));
TCCR0B |= (BV(CS00));
break;
}
case (PRESCALER_8): {
TCCR0B |= (_BV(CS01));
TCCR0B |= (BV(CS01));
break;
}
case (PRESCALER_64): {
TCCR0B |= (_BV(CS01) | _BV(CS00));
TCCR0B |= (BV(CS01) | BV(CS00));
break;
}
case (PRESCALER_256): {
TCCR0B |= (_BV(CS02));
TCCR0B |= (BV(CS02));
break;
}
case (PRESCALER_1024): {
TCCR0B |= (_BV(CS02) | _BV(CS00));
TCCR0B |= (BV(CS02) | BV(CS00));
break;
}
case (PRESCALER_OFF): {
@ -49,41 +49,41 @@ static inline void t0_set_ocr(enum e_timer_output output, uint8_t value) {
static inline void t0_set_out_mode(enum e_timer_output output, enum e_timer_output_mode mode) {
if (output & TO_A) {
TCCR0A &= ~(_BV(COM0A1) | _BV(COM0A0));
TCCR0A &= ~(BV(COM0A1) | BV(COM0A0));
switch (mode) {
case (TOM_00): {
break;
}
case (TOM_10): {
TCCR0A |= (_BV(COM0A1));
TCCR0A |= (BV(COM0A1));
break;
}
case (TOM_01): {
TCCR0A |= (_BV(COM0A0));
TCCR0A |= (BV(COM0A0));
break;
}
case (TOM_11): {
TCCR0A |= (_BV(COM0A1) | _BV(COM0A0));
TCCR0A |= (BV(COM0A1) | BV(COM0A0));
break;
}
}
}
if (output & TO_B) {
TCCR0A &= ~(_BV(COM0B1) | _BV(COM0B0));
TCCR0A &= ~(BV(COM0B1) | BV(COM0B0));
switch (mode) {
case (TOM_00): {
break;
}
case (TOM_10): {
TCCR0A |= (_BV(COM0B1));
TCCR0A |= (BV(COM0B1));
break;
}
case (TOM_01): {
TCCR0A |= (_BV(COM0B0));
TCCR0A |= (BV(COM0B0));
break;
}
case (TOM_11): {
TCCR0A |= (_BV(COM0B1) | _BV(COM0B0));
TCCR0A |= (BV(COM0B1) | BV(COM0B0));
break;
}
}
@ -98,15 +98,15 @@ static inline void t0_set_out_mode(enum e_timer_output output, enum e_timer_outp
/*
// OC2B = PD3 → output
DDRD |= _BV(DDD3) | _BV(DDD5) | _BV(DDD6);
DDRD |= BV(DDD3) | BV(DDD5) | BV(DDD6);
// Fast PWM (8-bit): WGM22:0 = 0b011
TCCR0A = _BV(WGM00) | _BV(WGM01);
TCCR0A |= _BV(COM0B1);
TCCR0A = BV(WGM00) | BV(WGM01);
TCCR0A |= BV(COM0B1);
// 50% duty cycle
OCR0B = 128;
// Start timer, prescaler = 64
TCCR0B = _BV(CS02);
TCCR0B = BV(CS02);
*/

38
ex00/include/timer2.h
View file

@ -8,30 +8,30 @@
static inline void t2_init_fpwm_3(e_timer_prescaler prescaler) {
// Fast PWM (8-bit): WGM22:0 = 0b011
TCCR2A = _BV(WGM20) | _BV(WGM21);
TCCR2A = BV(WGM20) | BV(WGM21);
// reset to zero -> timer off
TCCR2B &= ~(_BV(CS22) | _BV(CS21) | _BV(CS20));
TCCR2B &= ~(BV(CS22) | BV(CS21) | BV(CS20));
// set the correct prescaler
switch (prescaler) {
case (PRESCALER_1): {
TCCR2B |= (_BV(CS20));
TCCR2B |= (BV(CS20));
break;
}
case (PRESCALER_8): {
TCCR2B |= (_BV(CS21));
TCCR2B |= (BV(CS21));
break;
}
case (PRESCALER_64): {
TCCR2B |= (_BV(CS21) | _BV(CS20));
TCCR2B |= (BV(CS21) | BV(CS20));
break;
}
case (PRESCALER_256): {
TCCR2B |= (_BV(CS22));
TCCR2B |= (BV(CS22));
break;
}
case (PRESCALER_1024): {
TCCR2B |= (_BV(CS22) | _BV(CS20));
TCCR2B |= (BV(CS22) | BV(CS20));
break;
}
case (PRESCALER_OFF): {
@ -49,41 +49,41 @@ static inline void t2_set_ocr(enum e_timer_output output, uint8_t value) {
static inline void t2_set_out_mode(enum e_timer_output output, enum e_timer_output_mode mode) {
if (output & TO_A) {
TCCR2A &= ~(_BV(COM2A1) | _BV(COM2A0));
TCCR2A &= ~(BV(COM2A1) | BV(COM2A0));
switch (mode) {
case (TOM_00): {
break;
}
case (TOM_10): {
TCCR2A |= (_BV(COM2A1));
TCCR2A |= (BV(COM2A1));
break;
}
case (TOM_01): {
TCCR2A |= (_BV(COM2A0));
TCCR2A |= (BV(COM2A0));
break;
}
case (TOM_11): {
TCCR2A |= (_BV(COM2A1) | _BV(COM2A0));
TCCR2A |= (BV(COM2A1) | BV(COM2A0));
break;
}
}
}
if (output & TO_B) {
TCCR2A &= ~(_BV(COM2B1) | _BV(COM2B0));
TCCR2A &= ~(BV(COM2B1) | BV(COM2B0));
switch (mode) {
case (TOM_00): {
break;
}
case (TOM_10): {
TCCR2A |= (_BV(COM2B1));
TCCR2A |= (BV(COM2B1));
break;
}
case (TOM_01): {
TCCR2A |= (_BV(COM2B0));
TCCR2A |= (BV(COM2B0));
break;
}
case (TOM_11): {
TCCR2A |= (_BV(COM2B1) | _BV(COM2B0));
TCCR2A |= (BV(COM2B1) | BV(COM2B0));
break;
}
}
@ -98,15 +98,15 @@ static inline void t2_set_out_mode(enum e_timer_output output, enum e_timer_outp
/*
// OC2B = PD3 → output
DDRD |= _BV(DDD3) | _BV(DDD5) | _BV(DDD6);
DDRD |= BV(DDD3) | BV(DDD5) | BV(DDD6);
// Fast PWM (8-bit): WGM22:0 = 0b011
TCCR2A = _BV(GM20) | _BV(GM21);
TCCR2A |= _BV(COM2B1);
TCCR2A = BV(GM20) | BV(GM21);
TCCR2A |= BV(COM2B1);
// 50% duty cycle
OCR0B = 128;
// Start timer, prescaler = 64
TCCR2B = _BV(CS22);
TCCR2B = BV(CS22);
*/

14
ex00/src/main.c
View file

@ -10,24 +10,24 @@
void __attribute__((signal, used)) __vector_1(void) {
my_cli();
_delay_ms(20);
PORTB ^= _BV(PB0);
PORTB ^= BV(PB0);
// clear the register "pending" bit
EIFR |= _BV(INTF0);
EIFR |= BV(INTF0);
my_sei();
}
int main(void) {
uart_init();
DDRB |= _BV(PB0);
DDRD &= ~_BV(PD2);
DDRB |= BV(PB0);
DDRD &= ~BV(PD2);
// Set INT0 to trigger on falling edge
EICRA &= ~(_BV(ISC00) | _BV(ISC01));
EICRA |= _BV(ISC01);
EICRA &= ~(BV(ISC00) | BV(ISC01));
EICRA |= BV(ISC01);
// yes we want the INT0 interupt !
EIMSK |= _BV(INT0);
EIMSK |= BV(INT0);
my_sei();

12
ex00/src/uart.c
View file

@ -14,27 +14,27 @@ void uart_init(void) {
UBRR0H = (uint8_t)(UBRR_VALUE >> 8);
UBRR0L = (uint8_t)(UBRR_VALUE);
UCSR0A |= _BV(U2X0);
UCSR0A |= BV(U2X0);
// Enable transmitter
UCSR0B = _BV(TXEN0) | _BV(RXEN0) | _BV(RXCIE0);
UCSR0B = BV(TXEN0) | BV(RXEN0) | BV(RXCIE0);
// Set frame format: 8 data bits, no parity, 1 stop bit
UCSR0C = _BV(UCSZ01) | _BV(UCSZ00);
UCSR0C = BV(UCSZ01) | BV(UCSZ00);
// Set TX (PD1) as output
DDRD |= _BV(PD1);
DDRD |= BV(PD1);
}
void uart_tx(char data) {
// wait for transmit buffer to be empty
while (!(UCSR0A & _BV(UDRE0)))
while (!(UCSR0A & BV(UDRE0)))
;
// load data into transmit register
UDR0 = data;
}
char uart_rx(void) {
while (!(UCSR0A & _BV(RXC0)))
while (!(UCSR0A & BV(RXC0)))
;
return UDR0;
}

1
ex01/include/interupt.h
View file

@ -2,6 +2,7 @@
#define INTERUPT_H
#include <avr/io.h>
#include "mystd.h"
static inline void my_sei(void) {
SREG |= _BV(SREG_I);

2
ex01/include/mystd.h
View file

@ -14,4 +14,6 @@ typedef uint8_t bool;
#define NULL ((void*)0)
#define BV(bit) (1 << bit)
#endif /* MYSTDINT_H */

19
ex01/src/main.c
View file

@ -11,29 +11,28 @@
#include "timer1.h"
#include "timer2.h"
volatile uint16_t duty = 0;
volatile int8_t direction = 1;
void __attribute__((signal, used)) __vector_14(void) {
static uint16_t duty = 0;
static int8_t direction = 1;
// update duty
duty += direction;
duty += direction;
if (duty == 999) {
direction = -1;
// PORTB ^= _BV(PB0) | _BV(PB2); // useful for debug
//PORTB ^= _BV(PB0) | _BV(PB2); // useful for debug
} else if (duty == 0) {
direction = 1;
// PORTB ^= _BV(PB0) | _BV(PB2); // useful for debug
//PORTB ^= _BV(PB0) | _BV(PB2); // useful for debug
}
t1_set_ocr(TO_A, duty);
}
int main(void) {
// uart_init(); // no uart needed here :D
//uart_init(); // no uart needed here :D
DDRB |= _BV(PB0);
// DDRB |= _BV(PB1) | _BV(PD2);
// PORTB |= _BV(PD2);
DDRB |= _BV(PB1);
//DDRB |= _BV(PB0) | _BV(PD2);
//PORTB |= _BV(PD2);
t0_init_ctc_2(PRESCALER_64);
t0_set_ocr(TO_A, 250); // 64 * 150 * 1000 =

2
ex02/Makefile
View file

@ -1,6 +1,6 @@
# Makefile
MCU=atmega328p
F_CPU=16000000
F_CPU=16000000UL
CC=avr-gcc
OBJCOPY=avr-objcopy
WFLAGS=-Wall -Wextra

5
ex02/include/interupt.h
View file

@ -2,13 +2,14 @@
#define INTERUPT_H
#include <avr/io.h>
#include "mystd.h"
static inline void my_sei(void) {
SREG |= _BV(SREG_I);
SREG |= BV(SREG_I);
}
static inline void my_cli(void) {
SREG &= ~_BV(SREG_I);
SREG &= ~BV(SREG_I);
}
#endif /* INTERUPT_H */

2
ex02/include/mystd.h
View file

@ -14,4 +14,6 @@ typedef uint8_t bool;
#define NULL ((void*)0)
#define BV(bit) (1 << bit)
#endif /* MYSTDINT_H */

64
ex02/include/timer0.h
View file

@ -8,30 +8,30 @@
static inline void t0_init_ctc_2(e_timer_prescaler prescaler) {
// Fast PWM (8-bit): WGM22:0 = 0b011
TCCR0A = _BV(WGM01);
TCCR0A = BV(WGM01);
// reset to zero -> timer off
TCCR0B &= ~(_BV(CS02) | _BV(CS01) | _BV(CS00));
TCCR0B &= ~(BV(CS02) | BV(CS01) | BV(CS00));
// set the correct prescaler
switch (prescaler) {
case (PRESCALER_1): {
TCCR0B |= (_BV(CS00));
TCCR0B |= (BV(CS00));
break;
}
case (PRESCALER_8): {
TCCR0B |= (_BV(CS01));
TCCR0B |= (BV(CS01));
break;
}
case (PRESCALER_64): {
TCCR0B |= (_BV(CS01) | _BV(CS00));
TCCR0B |= (BV(CS01) | BV(CS00));
break;
}
case (PRESCALER_256): {
TCCR0B |= (_BV(CS02));
TCCR0B |= (BV(CS02));
break;
}
case (PRESCALER_1024): {
TCCR0B |= (_BV(CS02) | _BV(CS00));
TCCR0B |= (BV(CS02) | BV(CS00));
break;
}
case (PRESCALER_OFF): {
@ -42,30 +42,30 @@ static inline void t0_init_ctc_2(e_timer_prescaler prescaler) {
static inline void t0_init_fpwm_3(e_timer_prescaler prescaler) {
// Fast PWM (8-bit): WGM22:0 = 0b011
TCCR0A = _BV(WGM00) | _BV(WGM01);
TCCR0A = BV(WGM00) | BV(WGM01);
// reset to zero -> timer off
TCCR0B &= ~(_BV(CS02) | _BV(CS01) | _BV(CS00));
TCCR0B &= ~(BV(CS02) | BV(CS01) | BV(CS00));
// set the correct prescaler
switch (prescaler) {
case (PRESCALER_1): {
TCCR0B |= (_BV(CS00));
TCCR0B |= (BV(CS00));
break;
}
case (PRESCALER_8): {
TCCR0B |= (_BV(CS01));
TCCR0B |= (BV(CS01));
break;
}
case (PRESCALER_64): {
TCCR0B |= (_BV(CS01) | _BV(CS00));
TCCR0B |= (BV(CS01) | BV(CS00));
break;
}
case (PRESCALER_256): {
TCCR0B |= (_BV(CS02));
TCCR0B |= (BV(CS02));
break;
}
case (PRESCALER_1024): {
TCCR0B |= (_BV(CS02) | _BV(CS00));
TCCR0B |= (BV(CS02) | BV(CS00));
break;
}
case (PRESCALER_OFF): {
@ -76,23 +76,23 @@ static inline void t0_init_fpwm_3(e_timer_prescaler prescaler) {
static inline void t0_overflow_interrupt(bool enable) {
if (enable)
TIMSK0 |= _BV(TOIE0);
TIMSK0 |= BV(TOIE0);
else
TIMSK0 &= ~_BV(TOIE0);
TIMSK0 &= ~BV(TOIE0);
}
static inline void t0_interrupt(enum e_timer_output output, bool enable) {
if (output & TO_A) {
if (enable)
TIMSK0 |= _BV(OCIE0A);
TIMSK0 |= BV(OCIE0A);
else
TIMSK0 &= ~_BV(OCIE0A);
TIMSK0 &= ~BV(OCIE0A);
}
if (output & TO_B) {
if (enable)
TIMSK0 |= _BV(OCIE0B);
TIMSK0 |= BV(OCIE0B);
else
TIMSK0 &= ~_BV(OCIE0B);
TIMSK0 &= ~BV(OCIE0B);
}
}
@ -105,41 +105,41 @@ static inline void t0_set_ocr(enum e_timer_output output, uint8_t value) {
static inline void t0_set_out_mode(enum e_timer_output output, enum e_timer_output_mode mode) {
if (output & TO_A) {
TCCR0A &= ~(_BV(COM0A1) | _BV(COM0A0));
TCCR0A &= ~(BV(COM0A1) | BV(COM0A0));
switch (mode) {
case (TOM_00): {
break;
}
case (TOM_10): {
TCCR0A |= (_BV(COM0A1));
TCCR0A |= (BV(COM0A1));
break;
}
case (TOM_01): {
TCCR0A |= (_BV(COM0A0));
TCCR0A |= (BV(COM0A0));
break;
}
case (TOM_11): {
TCCR0A |= (_BV(COM0A1) | _BV(COM0A0));
TCCR0A |= (BV(COM0A1) | BV(COM0A0));
break;
}
}
}
if (output & TO_B) {
TCCR0A &= ~(_BV(COM0B1) | _BV(COM0B0));
TCCR0A &= ~(BV(COM0B1) | BV(COM0B0));
switch (mode) {
case (TOM_00): {
break;
}
case (TOM_10): {
TCCR0A |= (_BV(COM0B1));
TCCR0A |= (BV(COM0B1));
break;
}
case (TOM_01): {
TCCR0A |= (_BV(COM0B0));
TCCR0A |= (BV(COM0B0));
break;
}
case (TOM_11): {
TCCR0A |= (_BV(COM0B1) | _BV(COM0B0));
TCCR0A |= (BV(COM0B1) | BV(COM0B0));
break;
}
}
@ -154,15 +154,15 @@ static inline void t0_set_out_mode(enum e_timer_output output, enum e_timer_outp
/*
// OC2B = PD3 → output
DDRD |= _BV(DDD3) | _BV(DDD5) | _BV(DDD6);
DDRD |= BV(DDD3) | BV(DDD5) | BV(DDD6);
// Fast PWM (8-bit): WGM22:0 = 0b011
TCCR0A = _BV(WGM00) | _BV(WGM01);
TCCR0A |= _BV(COM0B1);
TCCR0A = BV(WGM00) | BV(WGM01);
TCCR0A |= BV(COM0B1);
// 50% duty cycle
OCR0B = 128;
// Start timer, prescaler = 64
TCCR0B = _BV(CS02);
TCCR0B = BV(CS02);
*/

54
ex02/include/timer1.h
View file

@ -8,29 +8,29 @@
static inline void t1_init_fpwm_14(e_timer_prescaler prescaler) {
// Fast PWM (8-bit): WGM22:0 = 0b011
TCCR1A = _BV(WGM11) | _BV(WGM12);
TCCR1B = _BV(WGM13);
TCCR1A = BV(WGM11) | BV(WGM12);
TCCR1B = BV(WGM13);
// set the correct prescaler
switch (prescaler) {
case (PRESCALER_1): {
TCCR1B |= (_BV(CS10));
TCCR1B |= (BV(CS10));
break;
}
case (PRESCALER_8): {
TCCR1B |= (_BV(CS11));
TCCR1B |= (BV(CS11));
break;
}
case (PRESCALER_64): {
TCCR1B |= (_BV(CS11) | _BV(CS10));
TCCR1B |= (BV(CS11) | BV(CS10));
break;
}
case (PRESCALER_256): {
TCCR1B |= (_BV(CS12));
TCCR1B |= (BV(CS12));
break;
}
case (PRESCALER_1024): {
TCCR1B |= (_BV(CS12) | _BV(CS10));
TCCR1B |= (BV(CS12) | BV(CS10));
break;
}
case (PRESCALER_OFF): {
@ -41,29 +41,29 @@ static inline void t1_init_fpwm_14(e_timer_prescaler prescaler) {
static inline void t1_init_ctc_4(e_timer_prescaler prescaler) {
// CTC mode 4
TCCR1A = _BV(WGM12);
TCCR1A = BV(WGM12);
TCCR1B = 0;
// set the correct prescaler
switch (prescaler) {
case (PRESCALER_1): {
TCCR1B |= (_BV(CS10));
TCCR1B |= (BV(CS10));
break;
}
case (PRESCALER_8): {
TCCR1B |= (_BV(CS11));
TCCR1B |= (BV(CS11));
break;
}
case (PRESCALER_64): {
TCCR1B |= (_BV(CS11) | _BV(CS10));
TCCR1B |= (BV(CS11) | BV(CS10));
break;
}
case (PRESCALER_256): {
TCCR1B |= (_BV(CS12));
TCCR1B |= (BV(CS12));
break;
}
case (PRESCALER_1024): {
TCCR1B |= (_BV(CS12) | _BV(CS10));
TCCR1B |= (BV(CS12) | BV(CS10));
break;
}
case (PRESCALER_OFF): {
@ -82,23 +82,23 @@ static inline void t1_set_icr1(uint16_t value) {
static inline void t1_overflow_interrupt(bool enable) {
if (enable)
TIMSK1 |= _BV(TOIE1);
TIMSK1 |= BV(TOIE1);
else
TIMSK1 &= ~_BV(TOIE1);
TIMSK1 &= ~BV(TOIE1);
}
static inline void t1_interrupt(enum e_timer_output output, bool enable) {
if (output & TO_A) {
if (enable)
TIMSK1 |= _BV(OCIE1A);
TIMSK1 |= BV(OCIE1A);
else
TIMSK1 &= ~_BV(OCIE1A);
TIMSK1 &= ~BV(OCIE1A);
}
if (output & TO_B) {
if (enable)
TIMSK1 |= _BV(OCIE1B);
TIMSK1 |= BV(OCIE1B);
else
TIMSK1 &= ~_BV(OCIE1B);
TIMSK1 &= ~BV(OCIE1B);
}
}
@ -111,41 +111,41 @@ static inline void t1_set_ocr(enum e_timer_output output, uint16_t value) {
static inline void t1_set_out_mode(enum e_timer_output output, enum e_timer_output_mode mode) {
if (output & TO_A) {
TCCR1A &= ~(_BV(COM1A1) | _BV(COM1A0));
TCCR1A &= ~(BV(COM1A1) | BV(COM1A0));
switch (mode) {
case (TOM_00): {
break;
}
case (TOM_10): {
TCCR1A |= (_BV(COM1A1));
TCCR1A |= (BV(COM1A1));
break;
}
case (TOM_01): {
TCCR1A |= (_BV(COM1A0));
TCCR1A |= (BV(COM1A0));
break;
}
case (TOM_11): {
TCCR1A |= (_BV(COM1A1) | _BV(COM1A0));
TCCR1A |= (BV(COM1A1) | BV(COM1A0));
break;
}
}
}
if (output & TO_B) {
TCCR1A &= ~(_BV(COM1B1) | _BV(COM1B0));
TCCR1A &= ~(BV(COM1B1) | BV(COM1B0));
switch (mode) {
case (TOM_00): {
break;
}
case (TOM_10): {
TCCR1A |= (_BV(COM1B1));
TCCR1A |= (BV(COM1B1));
break;
}
case (TOM_01): {
TCCR1A |= (_BV(COM1B0));
TCCR1A |= (BV(COM1B0));
break;
}
case (TOM_11): {
TCCR1A |= (_BV(COM1B1) | _BV(COM1B0));
TCCR1A |= (BV(COM1B1) | BV(COM1B0));
break;
}
}

50
ex02/include/timer2.h
View file

@ -8,30 +8,30 @@
static inline void t2_init_fpwm_3(e_timer_prescaler prescaler) {
// Fast PWM (8-bit): WGM22:0 = 0b011
TCCR2A = _BV(WGM20) | _BV(WGM21);
TCCR2A = BV(WGM20) | BV(WGM21);
// reset to zero -> timer off
TCCR2B &= ~(_BV(CS22) | _BV(CS21) | _BV(CS20));
TCCR2B &= ~(BV(CS22) | BV(CS21) | BV(CS20));
// set the correct prescaler
switch (prescaler) {
case (PRESCALER_1): {
TCCR2B |= (_BV(CS20));
TCCR2B |= (BV(CS20));
break;
}
case (PRESCALER_8): {
TCCR2B |= (_BV(CS21));
TCCR2B |= (BV(CS21));
break;
}
case (PRESCALER_64): {
TCCR2B |= (_BV(CS21) | _BV(CS20));
TCCR2B |= (BV(CS21) | BV(CS20));
break;
}
case (PRESCALER_256): {
TCCR2B |= (_BV(CS22));
TCCR2B |= (BV(CS22));
break;
}
case (PRESCALER_1024): {
TCCR2B |= (_BV(CS22) | _BV(CS20));
TCCR2B |= (BV(CS22) | BV(CS20));
break;
}
case (PRESCALER_OFF): {
@ -42,23 +42,23 @@ static inline void t2_init_fpwm_3(e_timer_prescaler prescaler) {
static inline void t2_overflow_interrupt(bool enable) {
if (enable)
TIMSK2 |= _BV(TOIE2);
TIMSK2 |= BV(TOIE2);
else
TIMSK2 &= ~_BV(TOIE2);
TIMSK2 &= ~BV(TOIE2);
}
static inline void t2_interrupt(enum e_timer_output output, bool enable) {
if (output & TO_A) {
if (enable)
TIMSK2 |= _BV(OCIE2A);
TIMSK2 |= BV(OCIE2A);
else
TIMSK2 &= ~_BV(OCIE2A);
TIMSK2 &= ~BV(OCIE2A);
}
if (output & TO_B) {
if (enable)
TIMSK2 |= _BV(OCIE2B);
TIMSK2 |= BV(OCIE2B);
else
TIMSK2 &= ~_BV(OCIE2B);
TIMSK2 &= ~BV(OCIE2B);
}
}
@ -71,41 +71,41 @@ static inline void t2_set_ocr(enum e_timer_output output, uint8_t value) {
static inline void t2_set_out_mode(enum e_timer_output output, enum e_timer_output_mode mode) {
if (output & TO_A) {
TCCR2A &= ~(_BV(COM2A1) | _BV(COM2A0));
TCCR2A &= ~(BV(COM2A1) | BV(COM2A0));
switch (mode) {
case (TOM_00): {
break;
}
case (TOM_10): {
TCCR2A |= (_BV(COM2A1));
TCCR2A |= (BV(COM2A1));
break;
}
case (TOM_01): {
TCCR2A |= (_BV(COM2A0));
TCCR2A |= (BV(COM2A0));
break;
}
case (TOM_11): {
TCCR2A |= (_BV(COM2A1) | _BV(COM2A0));
TCCR2A |= (BV(COM2A1) | BV(COM2A0));
break;
}
}
}
if (output & TO_B) {
TCCR2A &= ~(_BV(COM2B1) | _BV(COM2B0));
TCCR2A &= ~(BV(COM2B1) | BV(COM2B0));
switch (mode) {
case (TOM_00): {
break;
}
case (TOM_10): {
TCCR2A |= (_BV(COM2B1));
TCCR2A |= (BV(COM2B1));
break;
}
case (TOM_01): {
TCCR2A |= (_BV(COM2B0));
TCCR2A |= (BV(COM2B0));
break;
}
case (TOM_11): {
TCCR2A |= (_BV(COM2B1) | _BV(COM2B0));
TCCR2A |= (BV(COM2B1) | BV(COM2B0));
break;
}
}
@ -120,15 +120,15 @@ static inline void t2_set_out_mode(enum e_timer_output output, enum e_timer_outp
/*
// OC2B = PD3 → output
DDRD |= _BV(DDD3) | _BV(DDD5) | _BV(DDD6);
DDRD |= BV(DDD3) | BV(DDD5) | BV(DDD6);
// Fast PWM (8-bit): WGM22:0 = 0b011
TCCR2A = _BV(GM20) | _BV(GM21);
TCCR2A |= _BV(COM2B1);
TCCR2A = BV(GM20) | BV(GM21);
TCCR2A |= BV(COM2B1);
// 50% duty cycle
OCR0B = 128;
// Start timer, prescaler = 64
TCCR2B = _BV(CS22);
TCCR2B = BV(CS22);
*/

70
ex02/src/main.c
View file

@ -13,65 +13,47 @@
volatile uint8_t counter = 0;
#define LED_MASK (_BV(PB0) | _BV(PB1) | _BV(PB2) | _BV(PB4));
#define LED_MASK (BV(PB0) | BV(PB1) | BV(PB2) | BV(PB4));
#define BTN_MASK (BV(PD2) | BV(PD4))
void display_counter(void) {
PORTB &= ~LED_MASK;
PORTB |= ((counter & 0b111) | ((counter & 0b1000) << 1));
}
// interrupt for INT0 (external interrupt)
void __attribute__((signal, used)) __vector_1(void) {
EIMSK &= ~_BV(INT0);
EIFR |= _BV(INTF0);
// clear the register "pending" bit
t1_interrupt(TO_A, true);
counter++;
display_counter();
// uart_tx('I');
}
// external interupt
void __attribute__((signal, used)) __vector_5(void) {
EIMSK &= ~_BV(INT0);
EIFR |= _BV(INTF0);
// clear the register "pending" bit
t1_interrupt(TO_A, true);
counter++;
display_counter();
// uart_tx('I');
}
// timer1 compare match A
void __attribute__((signal, used)) __vector_11(void) {
static uint8_t prev_state = 0;
static uint8_t prev = 0;
//uart_tx('T');
uint8_t cur = PIND & BTN_MASK;
if (prev & BV(PD2) && !(cur & BV(PD2))) {
counter++;
display_counter();
}
if (prev & BV(PD4) && !(cur & BV(PD4))) {
counter--;
display_counter();
}
prev = cur;
}
// timer1 overflow match B
int main(void) {
uart_init();
//uart_init();
t1_init_ctc_4(PRESCALER_1024);
t1_interrupt(TO_B, true);
t1_set_ocr(TO_A, (F_CPU / (1024 * 20)) - 1);
t1_init_ctc_4(PRESCALER_8);
// every 20 ms -> trigger interrupt
t1_interrupt(TO_A, true);
t1_set_ocr(TO_A, (F_CPU / 8 / 1000) * 20);
DDRB |= LED_MASK;
DDRD &= ~(_BV(PD2) | _BV(PD4));
// Set INT0 to trigger on falling edge
EICRA &= ~(_BV(ISC00) | _BV(ISC01));
EICRA |= _BV(ISC01);
// yes we want the INT0 interupt !
EIMSK |= _BV(INT0);
// PD4
// Enable Pin Change Interrupt group for PORTD (PCINT[23:16])
PCICR |= (1 << PCIE2);
// Enable interrupt specifically for PD4 (PCINT20)
PCMSK2 |= (1 << PCINT20);
DDRB |= LED_MASK;
DDRD &= ~(BV(PD2) | BV(PD4));
my_sei();
while (1) {

12
ex02/src/uart.c
View file

@ -14,27 +14,27 @@ void uart_init(void) {
UBRR0H = (uint8_t)(UBRR_VALUE >> 8);
UBRR0L = (uint8_t)(UBRR_VALUE);
UCSR0A |= _BV(U2X0);
UCSR0A |= BV(U2X0);
// Enable transmitter
UCSR0B = _BV(TXEN0) | _BV(RXEN0);
UCSR0B = BV(TXEN0) | BV(RXEN0);
// Set frame format: 8 data bits, no parity, 1 stop bit
UCSR0C = _BV(UCSZ01) | _BV(UCSZ00);
UCSR0C = BV(UCSZ01) | BV(UCSZ00);
// Set TX (PD1) as output
DDRD |= _BV(PD1);
DDRD |= BV(PD1);
}
void uart_tx(char data) {
// wait for transmit buffer to be empty
while (!(UCSR0A & _BV(UDRE0)))
while (!(UCSR0A & BV(UDRE0)))
;
// load data into transmit register
UDR0 = data;
}
char uart_rx(void) {
while (!(UCSR0A & _BV(RXC0)))
while (!(UCSR0A & BV(RXC0)))
;
return UDR0;
}