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feat(ex02): done

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Maix0 2026-04-24 14:43:35 +02:00
parent b7580c043c
commit 0fe7dbdc0f
23 changed files with 1469 additions and 0 deletions
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70
ex02/include/eeprom.h Normal file
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#ifndef EEPROM_H
#define EEPROM_H
#include <avr/io.h>
#include "interupt.h"
#include "mystd.h"
static inline void eeprom_wait(void) {
while (EECR & BV(EEPE))
;
}
static inline void eeprom_write_single_nocheck(uint16_t addr, uint8_t data) {
uint8_t sreg_save = SREG;
my_cli();
// wait until eeprom is good to go !
eeprom_wait();
while (SPMCSR & BV(SPMEN))
;
// setup the (addr, data) pair
EEAR = addr;
EEDR = data;
// we set the EEPROM master write bit
EECR = (EECR & ~BV(EEPE)) | BV(EEMPE);
// within four cpu cycle, we need to set the EEPROM write bit, otherwise the writes doesnt work
// why 4 ? -> the master bit is reset after 4 cycles, and you need both to actually write
EECR |= BV(EEPE);
// this is the exact setup written in p32
// here the write should be done
SREG = sreg_save;
}
static inline uint8_t eeprom_read_single(uint16_t addr) {
uint8_t sreg_save = SREG;
my_cli();
eeprom_wait();
EEAR = addr;
EECR |= BV(EERE);
SREG = sreg_save;
return EEDR;
}
// true on error
static inline bool eeprom_write_single(uint16_t addr, uint8_t data) {
if (eeprom_read_single(addr) != data)
eeprom_write_single_nocheck(addr, data);
return (eeprom_read_single(addr) != data);
}
// true on error
static inline bool eeprom_write(uint16_t addr, const uint8_t* data, uint16_t length) {
for (uint16_t i = 0; i < length; i++) {
if (eeprom_write_single(addr + i, data[i]))
return true;
}
return false;
}
static inline void eeprom_read(uint16_t addr, uint8_t* data, uint16_t length) {
for (uint16_t i = 0; i < length; i++)
data[i] = eeprom_read_single(addr + i);
}
#endif /* EEPROM_H */