236 lines
7.9 KiB
C
236 lines
7.9 KiB
C
/*
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ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
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ChibiOS - Copyright (C) 2023..2024 HorrorTroll
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ChibiOS - Copyright (C) 2023..2024 Zhaqian
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef MCUCONF_H
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#define MCUCONF_H
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/*
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* AT32F415 drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 15...0 Lowest...Highest.
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*
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* DMA priorities:
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* 0...3 Lowest...Highest.
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*/
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#define AT32F415_MCUCONF
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/*
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* General settings.
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*/
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#define AT32_NO_INIT FALSE
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/*
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* HAL driver system settings.
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*/
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#define AT32_HICK_ENABLED TRUE
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#define AT32_LICK_ENABLED FALSE
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#define AT32_HEXT_ENABLED TRUE
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#define AT32_LEXT_ENABLED FALSE
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#define AT32_SCLKSEL AT32_SCLKSEL_PLL
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#define AT32_PLLRCS AT32_PLLRCS_HEXT
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#define AT32_PLLHEXTDIV AT32_PLLHEXTDIV_DIV1
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#define AT32_PLLCFGEN AT32_PLLCFGEN_SOLID
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#define AT32_PLLMULT_VALUE 18
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#define AT32_PLL_FR_VALUE 4
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#define AT32_PLL_MS_VALUE 1
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#define AT32_PLL_NS_VALUE 72
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#define AT32_AHBDIV AT32_AHBDIV_DIV1
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#define AT32_APB1DIV AT32_APB1DIV_DIV2
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#define AT32_APB2DIV AT32_APB2DIV_DIV2
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#define AT32_ADCDIV AT32_ADCDIV_DIV4
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#define AT32_USB_CLOCK_REQUIRED TRUE
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#define AT32_USBDIV AT32_USBDIV_DIV3
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#define AT32_CLKOUT_SEL AT32_CLKOUT_SEL_NOCLOCK
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#define AT32_CLKOUTDIV AT32_CLKOUTDIV_DIV1
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#define AT32_ERTCSEL AT32_ERTCSEL_HEXTDIV
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#define AT32_PVM_ENABLE FALSE
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#define AT32_PVMSEL AT32_PVMSEL_LEV1
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/*
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* IRQ system settings.
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*/
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#define AT32_IRQ_EXINT0_PRIORITY 6
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#define AT32_IRQ_EXINT1_PRIORITY 6
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#define AT32_IRQ_EXINT2_PRIORITY 6
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#define AT32_IRQ_EXINT3_PRIORITY 6
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#define AT32_IRQ_EXINT4_PRIORITY 6
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#define AT32_IRQ_EXINT5_9_PRIORITY 6
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#define AT32_IRQ_EXINT10_15_PRIORITY 6
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#define AT32_IRQ_EXINT16_PRIORITY 6
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#define AT32_IRQ_EXINT17_PRIORITY 15
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#define AT32_IRQ_EXINT18_PRIORITY 6
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#define AT32_IRQ_EXINT19_PRIORITY 6
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#define AT32_IRQ_EXINT20_PRIORITY 6
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#define AT32_IRQ_EXINT21_PRIORITY 15
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#define AT32_IRQ_EXINT22_PRIORITY 15
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#define AT32_IRQ_TMR1_BRK_TMR9_PRIORITY 7
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#define AT32_IRQ_TMR1_OVF_TMR10_PRIORITY 7
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#define AT32_IRQ_TMR1_HALL_TMR11_PRIORITY 7
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#define AT32_IRQ_TMR1_CH_PRIORITY 7
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#define AT32_IRQ_TMR2_PRIORITY 7
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#define AT32_IRQ_TMR3_PRIORITY 7
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#define AT32_IRQ_TMR4_PRIORITY 7
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#define AT32_IRQ_TMR5_PRIORITY 7
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#define AT32_IRQ_USART1_PRIORITY 12
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#define AT32_IRQ_USART2_PRIORITY 12
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#define AT32_IRQ_USART3_PRIORITY 12
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#define AT32_IRQ_UART4_PRIORITY 12
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#define AT32_IRQ_UART5_PRIORITY 12
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/*
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* ADC driver system settings.
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*/
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#define AT32_ADC_USE_ADC1 FALSE
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#define AT32_ADC_ADC1_DMA_PRIORITY 2
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#define AT32_ADC_ADC1_IRQ_PRIORITY 6
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/*
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* CAN driver system settings.
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*/
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#define AT32_CAN_USE_CAN1 FALSE
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#define AT32_CAN_CAN1_IRQ_PRIORITY 11
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/*
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* DMA driver system settings.
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*/
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#define AT32_DMA_USE_DMAMUX TRUE
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/*
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* GPT driver system settings.
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*/
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#define AT32_GPT_USE_TMR1 FALSE
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#define AT32_GPT_USE_TMR2 FALSE
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#define AT32_GPT_USE_TMR3 FALSE
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#define AT32_GPT_USE_TMR4 FALSE
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#define AT32_GPT_USE_TMR5 FALSE
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#define AT32_GPT_USE_TMR9 FALSE
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#define AT32_GPT_USE_TMR10 FALSE
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#define AT32_GPT_USE_TMR11 FALSE
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/*
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* I2C driver system settings.
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*/
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#define AT32_I2C_USE_I2C1 FALSE
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#define AT32_I2C_USE_I2C2 FALSE
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#define AT32_I2C_BUSY_TIMEOUT 50
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#define AT32_I2C_I2C1_IRQ_PRIORITY 5
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#define AT32_I2C_I2C2_IRQ_PRIORITY 5
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#define AT32_I2C_I2C1_DMA_PRIORITY 3
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#define AT32_I2C_I2C2_DMA_PRIORITY 3
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#define AT32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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/*
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* ICU driver system settings.
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*/
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#define AT32_ICU_USE_TMR1 FALSE
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#define AT32_ICU_USE_TMR2 FALSE
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#define AT32_ICU_USE_TMR3 FALSE
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#define AT32_ICU_USE_TMR4 FALSE
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#define AT32_ICU_USE_TMR5 FALSE
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#define AT32_ICU_USE_TMR9 FALSE
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#define AT32_ICU_USE_TMR10 FALSE
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#define AT32_ICU_USE_TMR11 FALSE
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/*
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* PWM driver system settings.
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*/
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#define AT32_PWM_USE_TMR1 FALSE
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#define AT32_PWM_USE_TMR2 FALSE
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#define AT32_PWM_USE_TMR3 FALSE
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#define AT32_PWM_USE_TMR4 FALSE
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#define AT32_PWM_USE_TMR5 FALSE
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#define AT32_PWM_USE_TMR9 FALSE
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#define AT32_PWM_USE_TMR10 FALSE
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#define AT32_PWM_USE_TMR11 FALSE
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/*
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* RTC driver system settings.
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*/
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#define AT32_ERTC_DIVA_VALUE 32
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#define AT32_ERTC_DIVB_VALUE 1024
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#define AT32_ERTC_CTRL_INIT 0
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#define AT32_ERTC_TAMP_INIT 0
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/*
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* SDC driver system settings.
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*/
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#define AT32_SDC_SDIO_DMA_PRIORITY 3
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#define AT32_SDC_SDIO_IRQ_PRIORITY 9
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#define AT32_SDC_WRITE_TIMEOUT_MS 1000
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#define AT32_SDC_READ_TIMEOUT_MS 1000
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#define AT32_SDC_CLOCK_ACTIVATION_DELAY 10
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#define AT32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
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/*
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* SERIAL driver system settings.
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*/
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#define AT32_SERIAL_USE_USART1 FALSE
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#define AT32_SERIAL_USE_USART2 FALSE
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#define AT32_SERIAL_USE_USART3 FALSE
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#define AT32_SERIAL_USE_UART4 FALSE
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#define AT32_SERIAL_USE_UART5 FALSE
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/*
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* SPI driver system settings.
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*/
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#define AT32_SPI_USE_SPI1 FALSE
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#define AT32_SPI_USE_SPI2 FALSE
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#define AT32_SPI_SPI1_DMA_PRIORITY 1
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#define AT32_SPI_SPI2_DMA_PRIORITY 1
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#define AT32_SPI_SPI1_IRQ_PRIORITY 10
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#define AT32_SPI_SPI2_IRQ_PRIORITY 10
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#define AT32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
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/*
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* ST driver system settings.
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*/
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#define AT32_ST_IRQ_PRIORITY 8
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#define AT32_ST_USE_TIMER 2
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/*
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* UART driver system settings.
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*/
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#define AT32_UART_USE_USART1 FALSE
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#define AT32_UART_USE_USART2 FALSE
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#define AT32_UART_USE_USART3 FALSE
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#define AT32_UART_USART1_DMA_PRIORITY 0
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#define AT32_UART_USART2_DMA_PRIORITY 0
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#define AT32_UART_USART3_DMA_PRIORITY 0
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#define AT32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
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/*
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* USB driver system settings.
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*/
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#define AT32_USB_USE_OTG1 TRUE
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#define AT32_USB_OTG1_IRQ_PRIORITY 14
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#define AT32_USB_OTG1_RX_FIFO_SIZE 512
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/*
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* WDG driver system settings.
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*/
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#define AT32_WDG_USE_WDT FALSE
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#endif /* MCUCONF_H */
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