2026-04-18 00:13:52 +02:00
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#ifndef TIMER1_H
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#define TIMER1_H
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#include <avr/io.h>
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#include "mystd.h"
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#include "timer_global.h"
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static inline void t1_init_fpwm_14(e_timer_prescaler prescaler) {
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// Fast PWM (8-bit): WGM22:0 = 0b011
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2026-04-19 15:38:04 +02:00
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TCCR1A = BV(WGM11) | BV(WGM12);
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TCCR1B = BV(WGM13);
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2026-04-18 00:13:52 +02:00
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// set the correct prescaler
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switch (prescaler) {
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case (PRESCALER_1): {
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2026-04-19 15:38:04 +02:00
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TCCR1B |= (BV(CS10));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (PRESCALER_8): {
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2026-04-19 15:38:04 +02:00
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TCCR1B |= (BV(CS11));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (PRESCALER_64): {
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2026-04-19 15:38:04 +02:00
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TCCR1B |= (BV(CS11) | BV(CS10));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (PRESCALER_256): {
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2026-04-19 15:38:04 +02:00
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TCCR1B |= (BV(CS12));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (PRESCALER_1024): {
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2026-04-19 15:38:04 +02:00
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TCCR1B |= (BV(CS12) | BV(CS10));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (PRESCALER_OFF): {
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break;
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}
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}
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}
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static inline void t1_init_ctc_4(e_timer_prescaler prescaler) {
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// CTC mode 4
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2026-04-19 15:38:04 +02:00
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TCCR1A = BV(WGM12);
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2026-04-18 00:13:52 +02:00
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TCCR1B = 0;
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// set the correct prescaler
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switch (prescaler) {
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case (PRESCALER_1): {
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2026-04-19 15:38:04 +02:00
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TCCR1B |= (BV(CS10));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (PRESCALER_8): {
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2026-04-19 15:38:04 +02:00
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TCCR1B |= (BV(CS11));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (PRESCALER_64): {
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2026-04-19 15:38:04 +02:00
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TCCR1B |= (BV(CS11) | BV(CS10));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (PRESCALER_256): {
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2026-04-19 15:38:04 +02:00
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TCCR1B |= (BV(CS12));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (PRESCALER_1024): {
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2026-04-19 15:38:04 +02:00
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TCCR1B |= (BV(CS12) | BV(CS10));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (PRESCALER_OFF): {
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break;
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}
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}
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}
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static inline void t1_set_counter(uint16_t val) {
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TCNT1 = val;
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}
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static inline void t1_set_icr1(uint16_t value) {
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ICR1 = value;
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}
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static inline void t1_overflow_interrupt(bool enable) {
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if (enable)
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2026-04-19 15:38:04 +02:00
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TIMSK1 |= BV(TOIE1);
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2026-04-18 00:13:52 +02:00
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else
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2026-04-19 15:38:04 +02:00
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TIMSK1 &= ~BV(TOIE1);
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2026-04-18 00:13:52 +02:00
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}
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static inline void t1_interrupt(enum e_timer_output output, bool enable) {
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if (output & TO_A) {
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if (enable)
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2026-04-19 15:38:04 +02:00
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TIMSK1 |= BV(OCIE1A);
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2026-04-18 00:13:52 +02:00
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else
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2026-04-19 15:38:04 +02:00
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TIMSK1 &= ~BV(OCIE1A);
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2026-04-18 00:13:52 +02:00
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}
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if (output & TO_B) {
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if (enable)
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2026-04-19 15:38:04 +02:00
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TIMSK1 |= BV(OCIE1B);
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2026-04-18 00:13:52 +02:00
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else
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2026-04-19 15:38:04 +02:00
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TIMSK1 &= ~BV(OCIE1B);
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2026-04-18 00:13:52 +02:00
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}
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}
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static inline void t1_set_ocr(enum e_timer_output output, uint16_t value) {
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if (output & TO_A)
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OCR1A = value;
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if (output & TO_B)
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OCR1B = value;
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}
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static inline void t1_set_out_mode(enum e_timer_output output, enum e_timer_output_mode mode) {
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if (output & TO_A) {
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2026-04-19 15:38:04 +02:00
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TCCR1A &= ~(BV(COM1A1) | BV(COM1A0));
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2026-04-18 00:13:52 +02:00
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switch (mode) {
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case (TOM_00): {
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break;
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}
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case (TOM_10): {
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2026-04-19 15:38:04 +02:00
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TCCR1A |= (BV(COM1A1));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (TOM_01): {
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2026-04-19 15:38:04 +02:00
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TCCR1A |= (BV(COM1A0));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (TOM_11): {
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2026-04-19 15:38:04 +02:00
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TCCR1A |= (BV(COM1A1) | BV(COM1A0));
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2026-04-18 00:13:52 +02:00
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break;
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}
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}
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}
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if (output & TO_B) {
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2026-04-19 15:38:04 +02:00
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TCCR1A &= ~(BV(COM1B1) | BV(COM1B0));
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2026-04-18 00:13:52 +02:00
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switch (mode) {
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case (TOM_00): {
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break;
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}
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case (TOM_10): {
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2026-04-19 15:38:04 +02:00
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TCCR1A |= (BV(COM1B1));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (TOM_01): {
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2026-04-19 15:38:04 +02:00
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TCCR1A |= (BV(COM1B0));
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2026-04-18 00:13:52 +02:00
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break;
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}
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case (TOM_11): {
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2026-04-19 15:38:04 +02:00
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TCCR1A |= (BV(COM1B1) | BV(COM1B0));
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2026-04-18 00:13:52 +02:00
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break;
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}
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}
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}
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}
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// OC2B => RED => PD3
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// OC0B => GREEN => PD5
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// OC0A => BLUE => PD6
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#endif /* TIMER1_H */
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